(1) Field of the Invention
This invention relates to a frequency division circuit and more particularly to a frequency division circuit suitable for use in an electronic timepiece utilizing field effect transistors.
(2) Technical Considerations and Prior Art
A frequency division circuit generally comprises an odd number of clock controllable delay circuits having a negative amplification coefficient and being connected in a closed ring circuit. For example, the frequency division circuit may include flip-flop circuits each including a data input from a latch circuit and an inverted output. This circuit requires two phase clock pulses for the purpose of writing an information signal ("0" or "1") into a flip-flop circuit in an earlier stage or into a flip-flop circuit in a later stage and to accurately store the written information. Furthermore, the flip-flop circuit in respective stages consumes substantial power in storing, inverting and amplifying the information from the preceding stage and for transmitting the amplified information to the succeeding stage. Further, in an electronic timepiece of high accuracy, where, for example, it is necessary to reduce a reference frequency of several MHz to less than 1 Hz, it is necessary to use a frequency division circuit having a high ratio of frequency division. In order to cause a plurality of flip-flop circuits to oscillate when connected in a ring, it is generally necessary to serially connect (2n + 1) flip-flop circuits or 2n flip-flop circuits and one inverting circuit, where n is an integer. When n is larger than 5, oscillations of various modes appear in the serially connected circuit, so that it becomes necessary to use a detection circuit or a mode locking circuit for the purpose of deriving only a specific oscillation mode as the ratio of frequency division increases.
For this reason, where a prior art frequency division circuit is applied to an electronic timepiece it is impossible to simplify the circuit in order to decrease the power consumption and minaturize the timepiece, both of which are highly desirable considerations in the design of electronic timepieces. Furthermore, the circuit for generating two phase clock pulses also consumes a great deal of power.